Design and Analysis of Low Power, Area Efficient Skip Logic for CSKA Circuit in Arithmetic Unit

被引：0

作者：

Vijayakumar, S. ^{[1
]}

Jayaprakasan, V. ^{[1
]}

Korah, Reeba ^{[2
]}

机构：

[1] SITAMS Autonomous, Dept ECE, Chittoor 517127, Andhra Pradesh, India

[2] Alliance Univ, Alliance Coll Engg & Design, Bangalore 562106, Karnataka, India

来源：

2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS) | 2018年

关键词：

Carry Skip Adder; CSKA; GDI MUX; Low Power; Skip Logic; ALU; CARRY-LOOKAHEAD ADDERS; DELAY OPTIMIZATION;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Processor cores of all the digital things have CPU with ALU as main block as a fact. Adder is the fundamental arithmetic component which performs considerable work. This article discusses the design, analysis of power optimized and area reduced Carry Skip Adder (CSKA). Area and Power are minimized with the help Hybrid GDI kind of MUX structure in skip logic of CSKA. The proposed one requires 39% low power consumption at the expense of 22% more delay than Transmission Gate (TG) based structure for skip logic. It's area in terms of cell count is negligibly smaller than CMOS MUX.

引用

页码：162 / 166

页数：5

共 50 条

[1] An Arithmetic and Logic Unit Optimized for Area and power
Dubey, Vivechana
Sairam, Ravimohan
[J]. 2014 FOURTH INTERNATIONAL CONFERENCE ON ADVANCED COMPUTING AND COMMUNICATION TECHNOLOGIES (ACCT 2014), 2014, : 330 - 334
[2] Low Power, Area Efficient FinFET Circuit Design
Wang, Michael C.
[J]. WCECS 2009: WORLD CONGRESS ON ENGINEERING AND COMPUTER SCIENCE, VOLS I AND II, 2009, : 164 - 168
[3] Design of an Area Efficient and Low Power MAC Unit
Kapse, Vinod
Jain, Aashmi
Pattanaik, Manisha
[J]. SMART TRENDS IN INFORMATION TECHNOLOGY AND COMPUTER COMMUNICATIONS, SMARTCOM 2016, 2016, 628 : 276 - 284
[4] Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA
Gupta, Nidhi
[J]. 2014 6TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND COMMUNICATION NETWORKS, 2014, : 913 - 916
[5] Power Efficient Arithmetic and Logical Unit Design on FPGA
Kaushik, Bhuvan
Anand, Vatsala
Yasmeen, Kainat
Kaur, Amanpreet
[J]. 2018 6TH EDITION OF INTERNATIONAL CONFERENCE ON WIRELESS NETWORKS & EMBEDDED SYSTEMS (WECON), 2018, : 112 - 115
[6] Design of high efficient low power static logic circuit using SG FinFET
Sridharan, Venkatesan Rameya
Alagarsamy, Manjunathan
Rajangam, Balamurugan
Sekar, Lalitha
[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2024, 111 (10) : 1613 - 1630
[7] Input synchronization in low power CMOS arithmetic circuit design
Fabian, CA
Ercegovac, MD
[J]. THIRTIETH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1997, : 172 - 176
[8] A CMOS adiabatic logic for low power circuit design
Song, HS
Kang, JK
[J]. PROCEEDINGS OF 2004 IEEE ASIA-PACIFIC CONFERENCE ON ADVANCED SYSTEM INTEGRATED CIRCUITS, 2004, : 348 - 351
[9] Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
Trapti Sharma
Laxmi Kumre
[J]. Circuits, Systems, and Signal Processing, 2020, 39 : 3265 - 3288
[10] Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology
Sharma, Trapti
Kumre, Laxmi
[J]. CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2020, 39 (07) : 3265 - 3288

← 1 2 3 4 5 →