Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory

Flash memory comprises of grid of cells arranged in a rectangular lattice. A cell is a floating gate and the information is stored as charge in these floating gates. A multi-level-cell (MLC) stores more than one bit per cell. Programming of a cell in NAND Flash is attained by Fowler-Nordhiem tunneling till the ideal programmed voltage is attained. However, due to programming time constraints, some tolerance is accepted and the actual programmed voltage is allowed to be within some range of the ideal value. The read level is a random variable with some distribution around the mean programming level. Errors occur during reads because of overlaps of the level distributions. If the raw bit error rate has to be kept low, the distributions must be narrow. One of the impairment which broadens the distributions is the capacitive coupling between neighboring cells. This phenomenon called as inter-cell-interference due to floating-gate to floating-gate coupling can be from mild to extreme. To combat this effect, constrained coding is a possible solution. Constrained coding entails forbidding certain adjacent-cell charge-level combinations. There can be various types of constrained codes, one type of constrained codes assumes that level information is available while decoding all pages [1]. However, due to read latency requirements, level information may not be available while reading all pages. In this paper, constrained codes are proposed which do not need level information while decoding all pages and hence the average read latency is reduced. Error propagation is a crucial degrading factor for constrained decoding and the codes proposed are robust to channel noise. A new decoding algorithm which keeps synchronization which is crucial to contain error propagation is also proposed.