Breaking the power-delay tradeoff: Design of low-power high-speed MOS current-mode logic circuits operating with reduced supply voltage

In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages. We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. We propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25 mu m, 0.18 mu m and 0.13 mu m CMOS).