Novel process for vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) fabrication

被引：6

作者：

Masahara, M ^{[1
]}

Matsukawa, T ^{[1
]}

Tanoue, H ^{[1
]}

Ishii, K ^{[1
]}

Liu, YX ^{[1
]}

Sakamoto, K ^{[1
]}

Kanemaru, S ^{[1
]}

Suzuki, E ^{[1
]}

机构：

[1] Natl Inst Adv Ind Sci & Technol, Nanoelectr Res Inst, Tsukuba, Ibaraki 3058568, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2003年 / 42卷 / 6B期

关键词：

vertical DG MOSFET; TMAH; orientation-dependent wet-etching; ion-bombardment-retarded etching; Si wall; symmetrical double side gate; etchback; planarization;

D O I：

10.1143/JJAP.42.4138

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A novel process to fabricate a vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) has been proposed. The etch rate of ion-beam exposed Si in a tetramethylammonium hydroxide (TMAH) solution was found to be significantly retarded. By utilizing this phenomenon and the orientation-dependent etching of the Si with a TMAH solution, a 16-nm-thick Si wall for a vertical channel of the DG MOSFET was successfully fabricated on the bulk Si substrate. By applying the etchback process, symmetrical poly-Si DG was formed on each side of the Si wall. A drain contact hole was opened self-aligned to the Si wall by combining a planarization and an etchback process with an electron-beam resist.

引用

页码：4138 / 4141

页数：4

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