Level conversion for dual-supply systems

被引：0

作者：

Ishihara, F ^{[1
]}

Sheikh, F ^{[1
]}

Nikolic, B ^{[1
]}

机构：

[1] Univ Calif Berkeley, Dept EECS, Berkeley, CA 94720 USA

来源：

ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2003年

关键词：

level conversion; dual-supply voltage; flip-flop;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Novel flip-flops presented in this paper incorporate a half-latch LC and a precharged LC. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% robustness improvement and 18% layout area reduction.

引用

页码：164 / 167

页数：4

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