Hot carrier reliability for 0.13μm CMOS technology with dual gate oxide thickness

被引：17

作者：

Lin, C ^{[1
]}

Biesemans, S ^{[1
]}

Han, LK ^{[1
]}

Houlihan, K ^{[1
]}

Schiml, T ^{[1
]}

Schruefer, K ^{[1
]}

Wann, C ^{[1
]}

Chen, J ^{[1
]}

Mahnkopf, R ^{[1
]}

机构：

[1] Infineon Technol, Hopewell Jct, NY 12533 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904276

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Different PMOS hot carrier degradation mechanisms are observed in a 0.13 mum CMOS technology with ultra-thin gate oxide. Surprisingly, the gate voltage plays a significant role in total Idsat degradation, even at low temperature (40 degreesC). Hole trapping instead of electron trapping is observed under max Idsat degradation condition for PMOS. It is also shown that nitrogen affects NMOS and PMOS hot carrier degradation differently.

引用

页码：135 / 138

页数：4

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