Time-domain modeling of an RF all-digital PLL

被引：30

作者：

Syllaios, Ioannis L. ^{[1
]}

Staszewski, Robert Bogdan ^{[2
]}

Balsara, Poras T. ^{[1
]}

机构：

[1] Univ Texas Dallas, Ctr Integrated Circuits & Syst, Richardson, TX 75083 USA

[2] Texas Instruments Inc, Digital RF Processor Grp, Dallas, TX 75243 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2008年 / 55卷 / 06期

关键词：

all-digital phase-locked loop (ADPLL); CMOS; digitally controlled-oscillator (DCO); event driven; GSM; mobile phones; phase detection; phase noise; simulation; time-domain modeling; time-to-digital-converter (TDC); wireless;

D O I：

10.1109/TCSII.2007.916845

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new phase-domain all-digital phase-locked loop (ADPLL) for RF wireless applications has recently been proposed and commercially demonstrated. In this brief, we propose time-domain modeling and simulation techniques of the ADPLL that are well suited for system analysis using high-level programming languages, e.g., Matlab. They are based on the event-driven principles inherent in hardware description languages, e.g., VHDL, and enable the development of accurate and time-efficient behavioral models. The proposed techniques are demonstrated and validated through experimental results for a GSM standard.

引用

页码：601 / 605

页数：5

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