The phase fluctuations of the clock signal generated in the digital frequency synthesis process

The article presents, the results of the phase fluctuation measurements of the clock signal generated in the digital frequency synthesis process. For this purpose, dedicated DCM blocks embedded in the field programmable gate array Virtex4 XC4VFX12 structure are used. Measurements allowed to choose the appropriate mode of operation of these units to get the reference clock signal characterized by the smallest random error. (The phase fluctuations of the clock signal generated in the digital frequency synthesis process).