Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

被引：19

作者：

Ebrahimi, Behzad ^{[1
]}

Rostami, Masoud ^{[1
]}

Afzali-Kusha, Ali ^{[1
]}

Pedram, Massoud ^{[1
]}

机构：

[1] Univ Tehran, Dept Elect & Comp Engn, Tehran 14395515, Iran

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 10期

基金：

美国国家科学基金会;

关键词：

Back-gate design; design for manufacturability; FinFET; process variations; SRAM; yield; ARRAY; CMOS;

D O I：

10.1109/TVLSI.2010.2059054

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.

引用

页码：1911 / 1916

页数：6

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