Reliable and high performance asymmetric FinFET SRAM cell using back-gate control

As the technology scales down, the performance characteristics are degraded and the reliability of digital circuits against soft error and aging effects are reduced. In this paper, we propose a reliable asymmetric FinFET 6T SRAM cell formed by the combination of tied-gate and independent-gate transistors. In the proposed design, we used a fixed value for the back gate voltages and utilized the back gate control method along with the built-in feedback. HSPICE simulations in 32 nm FinFET technology at V-DD = 0.9 V indicate that the proposed cell has the highest read SNM, read speed, write stability, and the least read power consumption amongst recently reported cells. Furthermore, our proposed SRAM structure is the best soft error resilient design and, with a low difference, has the second least hold and read stability degradations against aging effect induced by negative bias temperature instability in comparison with other SRAM cells considered in this paper. In addition, the results demonstrate the efficiency of our proposed cell against process and environmental variations.