SPICE-compatible modelling technique for simulating floating-gate transistors

被引：8
|
作者：
Rapp, S. J. [1 ]
McMillan, K. R. [1 ]
Graham, D. W. [1 ]
机构：
[1] W Virginia Univ, Lane Dept Comp Sci & Elect Engn, Morgantown, WV 26506 USA
来源：
ELECTRONICS LETTERS | 2011年 / 47卷 / 08期
关键词：
D O I：
10.1049/el.2011.0458
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A technique is introduced to enable the simulation of floating-gate transistors within standard analogue circuit simulators, such as SPICE. This technique can be used in all types of circuit simulations, ranging from DC sweeps to charge-modification scenarios. The technique is then used to simulate several analogue circuits, the results of which show strong agreement with identical circuits fabricated in standard CMOS processes.
引用
收藏
页码：483 / 485
页数：3
相关论文
共 50 条
  • [41] Improved linearity active resistors using MOS and Floating-Gate MOS transistors
    Popa, Cosmin
    [J]. EUROCON 2007: THE INTERNATIONAL CONFERENCE ON COMPUTER AS A TOOL, VOLS 1-6, 2007, : 39 - 45
  • [42] Efficiency and reliability of Fowler-Nordheim tunnelling in CMOS floating-gate transistors
    Rumberg, B.
    Graham, D. W.
    [J]. ELECTRONICS LETTERS, 2013, 49 (23) : 1484 - 1486
  • [43] A wide range charge-balancing circuit using floating-gate transistors
    Hu, Jingzhen
    Gordon, Christal
    [J]. 2007 ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-16, 2007, : 5696 - 5699
  • [44] A NONVOLATILE ANALOG NEURAL MEMORY USING FLOATING-GATE MOS-TRANSISTORS
    YANG, H
    SHEU, BJ
    LEE, JC
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1992, 2 (01) : 19 - 25
  • [45] Modeling multiple-input floating-gate transistors for analog signal processing
    RamirezAngulo, J
    GonzalezAltamirano, G
    Choi, SC
    [J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 2020 - 2023
  • [46] Glutamate sensing with enzyme-modified floating-gate field effect transistors
    Braeken, D.
    Rand, D. R.
    Andrei, A.
    Huys, R.
    Spira, M. E.
    Yitzchaik, S.
    Shappir, J.
    Borghs, G.
    Callewaert, G.
    Bartic, C.
    [J]. BIOSENSORS & BIOELECTRONICS, 2009, 24 (08): : 2384 - 2389
  • [47] A built-in-test scheme for evaluating the parameters of floating-gate MOS transistors
    Hou, AS
    [J]. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2005, 54 (03) : 988 - 995
  • [48] Run-time programming of analog circuits using floating-gate transistors
    Graham, David W.
    Hasler, Paul
    [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 3816 - +
  • [49] Robustness of the Floating-Gate technique in a very low-noise environment
    Postel-Pellerin, J.
    Micolau, G.
    Abbas, C.
    Chiquet, P.
    Cavaillou, A.
    [J]. 2014 INTERNATIONAL SEMICONDUCTOR CONFERENCE (CAS), 2014, : 287 - 290
  • [50] Computational Associative Memory with Amorphous Metal-Oxide Channel 3D NAND-Compatible Floating-Gate Transistors
    Sun, Chen
    Li, Chao
    Samanta, Subhranu
    Han, Kaizhen
    Zheng, Zijie
    Zhang, Jishen
    Kong, Qiwen
    Xu, Haiwen
    Zhou, Zuopu
    Chen, Yue
    Zhuo, Cheng
    Ni, Kai
    Yin, Xunzhao
    Gong, Xiao
    [J]. ADVANCED ELECTRONIC MATERIALS, 2022, 8 (12)
12345