Design of a practical fault-tolerant adder in QCA

Quantum-dot cellular automata (QCA) has emerged as an attractive alternative to CMOS technology in nanoscale era. QCA-based circuits often suffer from various types of manufacturing defects and variations, and therefore, are unreliable and error-prone. Hence, developing fault-tolerant circuits are essential for their reliable realizations. Design of QCA adders have been studied extensively due to its frequent use in the construction of several computing subsystems including arithmetic and logical units (ALUs). Most of the existing QCA adder designs have ignored fault-tolerance against various defects relevant to QCA. Although, a few of them have studied the behavior of their design in presence of some possible defects, poor defect coverage and/or low fault-tolerance make them unsuitable for practical realizations. In this paper, we propose a QCA adder that shows significant fault-tolerance against all types of cell misplacement defects such as cell omission, cell displacement, cell misalignment and extra/additional cell deposition. In order to judge practical realizability of the proposed design, we have compared it with the existing adders in terms of both fault-tolerance and other commonly accepted design metrics such as area, delay, complexity, cost of fabrication, and irreversible power dissipation. The detailed comparative study reveals that the proposed adder not only offers significantly high degree of fault-tolerance but also performs fairly well as compared to the existing adders with respect to other design metrics too, thereby ensures practical realizability of the proposed adder. (C) 2016 Elsevier Ltd. All rights reserved.