A 1-V CMOS output stage with high linearity

被引：0
|
作者：
Aloisi, W [1 ]
Giustolisi, G [1 ]
Palumbo, G [1 ]
机构：
[1] Univ Catania, DEES, I-95125 Catania, Italy
来源：
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I: ANALOG CIRCUITS AND SIGNAL PROCESSING | 2003年
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A CMOS low-voltage output stage based on a push-pull topology is proposed. It is driven by a differential signal and its symmetric topology provides excellent intrinsic linearity. It can work with a power supply as low as I V and when loaded with a 500-Omega resistor it exhibits negligible even harmonic components whilst odd components are maintained well below -20 dB up to 900 mV(pp) of the output signal. Moreover, the output stage includes a simple current control which accurately sets the bias condition.
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页码：225 / 228
页数：4
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