POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS

被引：0

作者：

Bucur, I. ^{[1
]}

Cupcea, N. ^{[1
]}

Stefanescu, C. ^{[1
]}

Surpateanu, A. ^{[1
]}

机构：

[1] Univ Politehn Bucuresti, Dept Comp Sci & Engn, Bucharest, Romania

来源：

CAS: 2009 INTERNATIONAL SEMICONDUCTOR CONFERENCE, VOLS 1 AND 2, PROCEEDINGS | 2009年

关键词：

spurious switching power; K-feasible cones; optimum depth; optimal area and power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper is presented a new approach for decreasing the spurious power consumption in K-LUT based FPGA implemented circuits. The approach is based on selective collapsing nodes in a direct acyclic graph (DAG) representing combinational or synchronous sequential circuits. It was used the simulation-based approach that estimates, using Monte Carlo experiment, the spurious switching activity of each net in the circuit. Traversing circuits in topological order, step by step best K-feasible cone are computed at the output of each node. Preserving the best depth of the circuits the mapping stage is done searching to minimize spurious switching power.

引用

页码：435 / 438

页数：4

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