A multi-standard video accelerator based on a vector architecture

被引：10

作者：

Chouliaras, VA ^{[1
]}

Nunez, JL

Mulvaney, DJ

Rovati, FS

Alfonso, D

机构：

[1] Univ Loughborough, Dept Elect & Elect Engn, Elect Syst Design Grp, Loughborough, Leics, England

[2] Univ Bristol, Dept Elect Engn, Bristol, Avon, England

[3] STMicroelect, Adv Syst Technol Labs, Agrate Brianza, Italy

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 2005年 / 51卷 / 01期

关键词：

MPEG2; MPEG4; H264; vector/SIMD accelerator; embedded RISC;

D O I：

10.1109/TCE.2005.1405714

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 mu m silicon process(1).

引用

页码：160 / 167

页数：8

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