Design, Fabrication and Characterization of TSV Interposer Integrated 3D Capacitor for SIP Applications

被引：4
|
作者：
Li, Jiwei [1 ]
Ma, Shenglin [1 ]
Liu, Huan [2 ]
Guan, Yong [2 ]
Chen, Jing [2 ]
Jin, Yufeng [2 ]
Wang, Wei [2 ]
Hu, Liulin [3 ]
He, Shuwei [3 ]
机构：
[1] Xiamen Univ, Dept Mech & Elect Engn, Xiamen 361005, Peoples R China
[2] Peking Univ, Shenzhen Grad Sch, Shenzhen 518055, Guangdong, Peoples R China
[3] Chengdu Ganide Technol Co Ltd, Chengdu 610000, Sichuan, Peoples R China
来源：
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年
基金：
中国国家自然科学基金;
关键词：
system-level package(SIP); TSV interposer; TSV capacitor; capacitance density; leakage current;
D O I：
10.1109/ECTC.2018.00296
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, TSV interposer integrated 3D high density capacitor is presented, which is featuring in a Metal-Insulation-Metal (MIM) structure on inside surface of blind TSVs array. A process is developed with Al2O3 as insulation layer deposited by Atomic Layer Deposition (ALD). With this process, TSV interposer integrated high density 3D capacitor sample is fabricated, and characterized in terms of capacitance density, leakage current, breakdown voltage, Self-resonant frequency (SRF) and Equivalent series Resistance (ESR). According to the experiment, it has a capacitance density of 5nF/mm(2) , a leakage current less than 2.5 mu A at a bias voltage below 10V and a breakdown voltage about 20V, a predicted ESR about W and a ESR about MHz. The reason is investigated with simulation results and optimization direction is assured.
引用
收藏
页码：1974 / 1980
页数：7
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