Design, Fabrication and Characterization of TSV Interposer Integrated 3D Capacitor for SIP Applications

被引：4
|
作者：
Li, Jiwei [1 ]
Ma, Shenglin [1 ]
Liu, Huan [2 ]
Guan, Yong [2 ]
Chen, Jing [2 ]
Jin, Yufeng [2 ]
Wang, Wei [2 ]
Hu, Liulin [3 ]
He, Shuwei [3 ]
机构：
[1] Xiamen Univ, Dept Mech & Elect Engn, Xiamen 361005, Peoples R China
[2] Peking Univ, Shenzhen Grad Sch, Shenzhen 518055, Guangdong, Peoples R China
[3] Chengdu Ganide Technol Co Ltd, Chengdu 610000, Sichuan, Peoples R China
来源：
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年
基金：
中国国家自然科学基金;
关键词：
system-level package(SIP); TSV interposer; TSV capacitor; capacitance density; leakage current;
D O I：
10.1109/ECTC.2018.00296
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, TSV interposer integrated 3D high density capacitor is presented, which is featuring in a Metal-Insulation-Metal (MIM) structure on inside surface of blind TSVs array. A process is developed with Al2O3 as insulation layer deposited by Atomic Layer Deposition (ALD). With this process, TSV interposer integrated high density 3D capacitor sample is fabricated, and characterized in terms of capacitance density, leakage current, breakdown voltage, Self-resonant frequency (SRF) and Equivalent series Resistance (ESR). According to the experiment, it has a capacitance density of 5nF/mm(2) , a leakage current less than 2.5 mu A at a bias voltage below 10V and a breakdown voltage about 20V, a predicted ESR about W and a ESR about MHz. The reason is investigated with simulation results and optimization direction is assured.
引用
收藏
页码：1974 / 1980
页数：7
相关论文
共 50 条
  • [31] Assembly Process and Reliability Assessment of TSV/RDL/IPD Interposer with Multi-Chip-Stacking for 3D IC Integration SiP
    Zhan, Chau-Jie
    Tzeng, Pei-Jer
    Lau, John H.
    Dai, Ming-Ji
    Chien, Heng-Chieh
    Lee, Ching-Kuan
    Wu, Shang-Tsai
    Kao, Kuo-Shu
    Huang, Shin-Yi
    Fan, Chia-Wen
    Chung, Su-Ching
    Huang, Yu-Wei
    Lin, Yu-Min
    Chang, Jing-Yao
    Yang, Tsung-Fu
    Chen, Tai-Hung
    Lo, Robert
    Kao, M. J.
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 548 - 554
  • [32] Thermal Analysis and Heat Dissipation Optimization of 3D Packaging with TSV Interposer
    Ma, He
    Yu, Daquan
    Wang, Jun
    2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012), 2012, : 699 - 704
  • [33] Physical and Electrical Characterization of 3D Embedded Capacitor: A High-density MIM Capacitor Embedded in TSV
    Lin, Ye
    Tan, Chuan Seng
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1956 - 1961
  • [34] Convergence of 3D integrated packaging and 3D TSV ICs
    Chhabra, Navjot
    SOLID STATE TECHNOLOGY, 2010, 53 (08) : 22 - 23
  • [35] Process and RF modelling of TSV last approach for 3D RF interposer
    Fuchs, C.
    Charbonnier, J.
    Cheramy, S.
    Cadix, L.
    Henry, D.
    Chausse, P.
    Hajji, O.
    Farcy, A.
    Garnier, G.
    Brunet-Manquat, C.
    Diaz, J.
    Anciant, R.
    Vincent, P.
    Sillon, N.
    Ancey, P.
    2011 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND MATERIALS FOR ADVANCED METALLIZATION (IITC/MAM), 2011,
  • [36] Fabrication Process of a TSV Interposer for Radio Frequency Chip with Integrated Passive Devices
    Meng, Wei
    Jin, Yufeng
    Guan, Yong
    Zeng, Qinghua
    Hen, Jing C.
    2016 17TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2016, : 1041 - 1044
  • [37] Fabrication and Characterization of Electrical Interconnects and Microfluidic Cooling for 3D ICS With Silicon Interposer
    Oh, Hanju
    Zhang, Yue
    Zheng, Li
    May, Gary S.
    Bakir, Muhannad S.
    HEAT TRANSFER ENGINEERING, 2016, 37 (11) : 903 - 911
  • [38] Fabrication and Packagig of Microbump Interconnections for 3D TSV
    Yoon, Seung Wook
    Ku, Jae Hoon
    Suthiwongsunthorn, Nathapong
    Marimuthu, Pandi Chelvarn
    Carson, Flynn
    2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 262 - +
  • [39] Design, Fabrication and Characterization of Surface Electrode Ion Trap Integrated with TSV
    Zhao, Peng
    Tao, Jing
    Li, Hong Yu
    Lim, Yu Dian
    Guidoni, Luca
    Tan, Chuan Seng
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 13 - 17
  • [40] Fabrication of 3D Packaging TSV using DRIE
    Puech, M.
    Thevenoud, J. M.
    Gruffat, J. M.
    Launay, N.
    Arnal, N.
    Godinat, P.
    DTIP 2008: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS, 2008, : 109 - 114
12345