ADVANCED N-CHANNEL LDMOS WITH ULTRALOW SPECIFIC ON-RESISTANCE BY 0.18 μm EPITAXIAL BCD TECHNOLOGY

被引:0
|
作者
Yao, Yao [1 ]
Hu, Linhui [2 ]
Wang, Gangning [2 ]
Pu, Shanon [2 ]
Lin, Min-Zhi [1 ]
Ye, Zhiyuan [1 ]
Wang, Peng-Fei [1 ]
机构
[1] Fudan Univ, Sch Microelect, Shanghai 200433, Peoples R China
[2] Semicond Mfg Int Corp, Shanghai 201203, Peoples R China
关键词
6; V;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An advanced n-channel LDMOS (nLDMOS) by 0.18 mu m epitaxial BCD Technology is proposed with the best-in-class performance. Thin drift region oxidation by independent LOCOS process is adopted and optimized to improve the trade-off between breakdown voltage (BV) and specific ON-resistance (R-on,R-sp). Both P-Body and N-Drift region vertical doping optimization is developed accordingly to improve the reliability of the device. Both 20 V and 30 V nLDMOS devices are designed, and experimental results show that ultralow Ron, sp has been demonstrated (i.e., R-on,R- sp = 6.5 m Omega center dot mm(2) for BV = 27.6 V, R-on,R- sp = 9.6 m Omega center dot mm(2) for BV = 37.3 V, respectively). Moreover, the electrical safe operating area (SOA) and hot-carrier injection (HCI) are also improved.
引用
收藏
页数:3
相关论文
共 50 条
  • [31] A new low specific on-resistance Hk-LDMOS with N-poly diode
    Deng, Jing
    Huang, Mingmin
    Cheng, Junji
    Lyu, Xinjiang
    Chen, Xingbi
    SUPERLATTICES AND MICROSTRUCTURES, 2017, 101 : 180 - 190
  • [32] Reducing specific on-resistance for a trench SOI LDMOS with L-shaped P/N pillars
    Guo, Jingwei
    Hu, Shengdong
    Wang, Jian'an
    Guo, Gang
    Liu, Chang
    Yang, Han
    Ran, Shenglong
    RESULTS IN PHYSICS, 2020, 18
  • [33] Analysis of hot carrier effects in a 0.35 μm high voltage n-channel LDMOS transistor
    Enichlmair, H.
    Carniello, S.
    Park, J. M.
    Minixhofer, R.
    MICROELECTRONICS RELIABILITY, 2007, 47 (9-11) : 1439 - 1443
  • [34] Novel Grid-Gate 16V-nLDMOS with a Low Specific On-Resistance of 4.7mΩ.mm2 Based on A Standard 0.18μm BCD Platform
    Wang, Jiawei
    Qiao, Ming
    Ma, Dingxiang
    Gao, Yue
    Zhang, Bo
    2024 36TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND IC S, ISPSD 2024, 2024, : 438 - 441
  • [35] Study of n-channel MOSFETs with an enclosed-gate layout in a 0.18 micron CMOS technology
    Chen, L
    Gingrich, DM
    2004 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-7, 2004, : 1344 - 1348
  • [36] Hot-carrier behaviour of a 0.35 μm high-voltage n-channel LDMOS transistor
    Park, J. M.
    Enichimair, H.
    Minixhofer, R.
    SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007, 2007, : 369 - 372
  • [37] An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars
    Yang, Dong
    Hu, Shengdong
    Lei, Jianmei
    Huang, Ye
    Yuan, Qi
    Jiang, Yuyu
    Guo, Jingwei
    Cheng, Kun
    Lin, Zhi
    Zhou, Xichuan
    Tang, Fang
    SUPERLATTICES AND MICROSTRUCTURES, 2017, 112 : 269 - 278
  • [38] BD180LV-0.18 μm BCD Technology with Best-in-Class LDMOS from 7V to 30V
    Ko, Kwang-Young
    Park, Il-Yong
    Choi, Yong-Keon
    Yoon, Chul-Jin
    Moon, Ju-Hyoung
    Park, Kyung-Min
    Lim, Hyon-Chol
    Park, Soon-Yeol
    Kim, Nam-Joo
    Yoo, Kwang-Dong
    Hutter, Lou N.
    2010 22ND INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2010, : 71 - 74
  • [39] A 0.35 μm 700 V BCD Technology with Self-Isolated and Non-Isolated Ultra-low Specific On-Resistance DB-nLDMOS
    Mao, Kun
    Qiao, Ming
    Jiang, Lingli
    Jiang, Huaping
    Li, Zehong
    Chen, Weizhong
    Li, Zhaoji
    Zhang, Bo
    2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD), 2013, : 397 - 400
  • [40] A 33V, 0.25mΩ-cm2 n-channel LDMOS in a 0.65μm smart power technology for 20-30V applications
    Parthasarathy, V
    Zhu, R
    Peterson, W
    Zunino, M
    Baird, R
    ISPSD '98 - PROCEEDINGS OF THE 10TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, 1998, : 61 - 64