A Customized Design of DRAM Controller for On-Chip 3D DRAM Stacking

被引:0
|
作者
Zhang, Tao [1 ]
Wang, Kui [2 ]
Feng, Yi [3 ]
Song, Xiaodi [2 ]
Duan, Lian [1 ]
Xie, Yuan [1 ]
Cheng, Xu [3 ]
Lin, Youn-Long [4 ]
机构
[1] Penn State Univ, Dept Comp Sci & Engn, University Pk, PA 16802 USA
[2] Peking Univ Unity Microsyst Technol Cp Ltd, Beijing, Peoples R China
[3] Peking Univ, Dept Comp Sci, Beijing, Peoples R China
[4] Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu, Taiwan
关键词
PROCESSORS; MEMORY;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
To address the "memory wall" challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins. To demonstrate the feasibility of 3D memory stacking, this paper introduces a customized 3D Double-Data-Rate (DDR) SDRAM controller design, which communicates with DRAM layers by TSVs. In addition, we propose a parallel access policy to further improve the performance. The 3D DDR controller is integrated in a 3D stacking System-on-Chip (SoC) architecture, where a high-bandwidth 3D DRAM chip is stacked on the top. The 3D SoC is divided into two logic layers with each having an area of 2.5 x 5.0mm(2), with a 3-layer 2Gb DRAM stacking. The whole chip has been fabricated in Chartered 130nm low-power process and Tezzaron's 3D bonding technology. The simulation result shows that the on-chip DRAM controller can run as fast as 133MHz and provide 4.25GB/s data bandwidth in a single channel and 8.5GB/s with parallel access policy. (1)
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页数:4
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