3D DRAM Design and Application to 3D Multicore Systems

被引：29

作者：

Sun, Hongbin ^{[1
]}

Liu, Jibang ^{[2
]}

Anigundi, Rakesh S.

Zheng, Nanning

Lu, Jian-Qiang ^{[2
]}

Rose, Kenneth ^{[2
]}

Zhang, Tong ^{[2
]}

机构：

[1] Xi An Jiao Tong Univ, Inst Artificial Intelligence & Robot, Sch Elect & Informat Engn, Xian 710049, Shaanxi, Peoples R China

[2] Rensselaer Polytech Inst, Dept Elect Comp & Syst Engn, Troy, NY 12181 USA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2009年 / 26卷 / 05期

基金：

美国国家科学基金会;

关键词：

3D integration; Computer architecture; Design and test; DRAM; Energy consumption; Memory hierarchy; Multicore; Packaging; Random access memory; Routing; Solid modeling; Three dimensional displays;

D O I：

10.1109/MDT.2009.105

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Editor's note:From a system architecture perspective, 3D technology can satisfy the high memory bandwidth demands that future multicore/manycore architectures require. This article presents a 3D DRAM architecture design and the potential for using 3D DRAM stacking for both L2 cache and main memory in 3D multicore architecture. © 2009 IEEE.

引用

页码：36 / 46

页数：11

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