Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture

This paper presents a novel asynchronous bit-serial architecture for multi-context field programmable VLSIs (MC-FPVLSI). Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed context-ID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed architecture is designed using 6-metal 1-poly 90nm CMOS process technology.