Multiplierless, folded 9/7-5/3 wavelet VLSI architecture

被引：38

作者：

Martina, Maurizio ^{[1
]}

Masera, Guido ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Elettron, CERCOM, I-10129 Turin, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2007年 / 54卷 / 09期

关键词：

filter bank (FB); JPEG2000; multiplierless implementation; VLSI; wavelet;

D O I：

10.1109/TCSII.2007.900354

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-mu m standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance.

引用

页码：770 / 774

页数：5

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