Modified lifting algorithm and VLSI architecture for the 9/7 wavelet filters

被引：0
|
作者：
Xiong, CG [1 ]
Gao, ZR [1 ]
Tian, JW [1 ]
Liu, R [1 ]
机构：
[1] Huazhong Univ Sci & Technol, State Key Lab Educ Commiss Image Proc & Intellige, Inst Pattern Recognit & Artificial Intelligence, Wuhan 430074, Hebei, Peoples R China
来源：
PROCEEDINGS OF THE 2004 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-7 | 2004年
关键词：
parallel lifting scheme; wavelet transform; VLSI architecture;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A new parallel-based lifting algorithm (PBLA) for the 9/7 filters, exploring the parallelism of arithmetic operations in each lifting step, was proposed in this paper. It shortened significantly the critical path of computation, and resulted in a fast VLSI implementation architecture. In comparison with the conventional lifting algorithm based implementation (CLABI), the latency is reduced by more than half from (4T(m) + 8T(alpha)) to (T-m + 4T(alpha)), which is competitive to that of convolution based implementation CBI, and can be further reduced to Tm by inserting 3 stages of pipeline. The experimental results demonstrate that the proposed architecture has good performances in both speed and area.
引用
收藏
页码：3826 / 3829
页数：4
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