3D IC Process Development for Enabling Chip-on-Chip and Chip on Wafer Multi-Stacking at Assembly

Along with the flow and the fundamental focus on 3D integration, is the study in enabling stacking as well as assessing the needs to make it comparable to current manufacturing standards. To do this we take a look on key essential elements of a manufacturing line and applying it to the stacking process. Key areas of focus is process stability, control and ability to reducing the bond parameters (time, temp and force). With this we take a look at the developments done to enable such a condition and allowing the gathering and analysis of relevant data for enabling chip-on-chip (CoC) and chip on-wafer (CoW) stacking in assembly production. CoC and CoW bonding is a stacking scheme in the 3D IC integration flow where diced top dies are bonded individually, using thermocompression bonding (TCB), directly over a whole bottom wafer or individual chips. These two methods have their advantages and disadvantages during assembly. One is to bond each chip only on another individual chips diced prior stacking, which is identified as CoC. Another is to place multiple chips in a single whole wafer then do the dicing afterwards. Both can be configured to adapt for multi-stacking. In this paper, we present the applicability of each process to actual production. We place side by side advantages and disadvantages for both methods with actual bond results. We also take a look on major parameters involved and innovative solutions used to address challenges. Coverage of this paper involves CoC and CoW stacking. Experiments are done on units using no-flow underfill (NUF) and wafer-level underfill (WLUF). The study covers learning's on the process development of die multi-stacking on 3D IC applications The paper will cover parameters, equipment and materials involved during the CoC and CoW bonding process. The goal of the paper is to show process development advances on 3D integration.