A CMOS analog neuro-chip with stochastic learning and multilevel weight storage

被引：0
|
作者：
Conti, M
Guaitini, G
Turchetti, C
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
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D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A CMOS analog neural network is described in this paper. The chip, fabricated in a 1.0 mu m CMOS technology, has a 2-dimension input vector, 16 neurons, 112 weights, each one with a multilevel storage circuit, 28 internal uncorrelated noise sources, a random weight change learning algorithm implemented on-chip, weight access capability.
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页码：1844 / 1847
页数：4
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