Discrete Wavelet Transform Implementation Based on FPGA

被引：0
|
作者：
Li, Juan [1 ]
Su, Binghua [1 ,2 ,3 ]
Yan, Yongming [2 ,3 ]
Jiang, Caigao [2 ,3 ]
机构：
[1] Beijing Inst Technol, Minist Educ China, Key Lab Photo Elect Imaging Technol & Syst, Beijing 100081, Peoples R China
[2] Informat Sch, Beijing, Peoples R China
[3] Inst Technol Zhuhai, Zhuhai 519085, Peoples R China
来源：
PROCEEDINGS OF 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING (ICSP) VOLS 1-3 | 2012年
关键词：
FPGA; discrete wavelet transform; Verilog HDL language;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a semi-cache parallel circuit structure which is based on FPGA process system combined with the existing Mallat discrete wavelet transform algorithm is introduced. The virtex-6 FPGA development board implements this structure in real-time, and the functional modules of DSP48E1 in the virtex-6 serves as the improvement of data accuracy. Modelsim is responsible for simulation of each module unit in Verilog HDL. Compared with the conventional algorithm, this architecture reduces half of the on-chip storage resources. Besides, in comparison with the performance of processing time on OMAP3530, Simulation results demonstrate that this state-of-art method shows more superiority.
引用
收藏
页码：439 / +
页数：3
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