Design and FPGA implementation of orthonormal discrete wavelet transforms

被引：0

作者：

Nibouche, M ^{[1
]}

Bouridane, A ^{[1
]}

Nibouche, O ^{[1
]}

Crookes, D ^{[1
]}

Boussekta, S ^{[1
]}

机构：

[1] Queens Univ Belfast, Image & Vis Syst Grp, Sch Comp Sci, Belfast BT7 1NN, Antrim, North Ireland

来源：

ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II | 2000年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

FPGA technology offers the potential for low cost, high performance for certain applications, including image processing. However, the programming model which FPGAs typically present to application developers is prohibitively low level. The purpose of this paper is to present a novel bit-serial architecture based on a time-interleaved structure. To overcome the problem of wait cycles within the structure, a second line of bit adders is provided. This allows the structure to use additional "dummy" cycles to deal with additional bits. The proposed architecture is modular and scalable, which allows a bit-level parameterisation. To assess the effectiveness of the approach the design has been implemented efficiently on the Xilinx 4000 series FPGAs.

引用

页码：312 / 315

页数：4

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