Design and FPGA implementation of othonormal inverse discrete wavelet transforms

被引：1

作者：

Nibouche, M ^{[1
]}

Bouridane, A ^{[1
]}

Nibouche, O ^{[1
]}

Belatreche, A ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Comp Sci, Image & Vis Syst Grp, Belfast BT7 1NN, Antrim, North Ireland

来源：

2001 IEEE THIRD WORKSHOP ON SIGNAL PROCESSING ADVANCES IN WIRELESS COMMUNICATIONS, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/SPAWC.2001.923924

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

FPGA technology offers the potential for low cost, high performance for certain applications, including signal and image processing. Although the programming model which, FPGAs typically present to application developers is prohibitively low level, they are good target devices for rapid prototyping. The purpose of this paper is to present a novel bit-serial structure dedicated to inverse discrete wavelet transforms based on a time-interleaved FIR filters. To overcome the problem of wait cycles within the structure, a second line of bit adders is provided. This allows the structure to use additional "dummy" cycles to deal with additional bits. The proposed structure is modular and scalable, which allows a bit-level parameterisation. To assess the effectiveness of the approach the design has been implemented efficiently on the Xilinx 4000 series FPGAs.

引用

页码：356 / 359

页数：4

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