Architecture-level performance estimation method based on system-level profiling

被引：5
|
作者：
Ueda, K [1 ]
Sakanushi, K [1 ]
Takeuchi, Y [1 ]
Imai, M [1 ]
机构：
[1] Osaka Univ, Grad Sch Informat Sci & Technol, Suita, Osaka 5650871, Japan
来源：
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 2005年 / 152卷 / 01期
关键词：
D O I：
10.1049/ip-cdt:20045057
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An architecture-level performance estimation method based on system-level profiling is proposed. The proposed method estimates the performance of the target architecture by the following procedures: system-level profiling; automatic construction of the execution order graph and execution dependency graph from the profiling information; and estimation of the system performance based on the graph analysis. The proposed method enables fast performance estimation because it can estimate the performance of various architectures from the same system-level profiling information. Experimental results show that the proposed estimation method is 2700 times faster than the architecture-level simulation.
引用
收藏
页码：12 / 19
页数：8
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