A pipelined 8x8 2-D forward DCT hardware architecture for H.264/AVC high profile encoder

被引:0
|
作者
da Silva, Thaisa Leal [1 ]
Diniz, Claudio Machado [1 ]
Vortmann, Joao Alberto [2 ]
Agostini, Luciano Volcan [2 ]
Susin, Altamiro Amadeu [1 ]
Bampi, Sergio [1 ]
机构
[1] Univ Fed Rio Grande do Sul, Microelect Grp, Porto Alegre, RS, Brazil
[2] Univ Fed Pelotas, Grp Architectures & Integrated Circuits, Pelotas, RS, Brazil
关键词
video compression; 8x8 2-D DCT; H.264/AVC standard; architectural design;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
This paper presents the hardware design of an W bi-dimensional Forward Discrete Cosine Transform used in the high profiles of the H.264/AVC video coding standard. The designed DCT is computed in a separate way as two 1-D transforms. It uses only add and shift operations, avoiding multiplications. The architecture contains one datapath for each 1-D DCT with a transpose buffer between them. The complete architecture was synthesized to Xilinx Virtex II - Pro and Altera Stratix II FPGAs and to TSMC 0.35 mu m standard-cells technology. The synthesis results show that the 2-D DCT transform architecture reached the necessary throughput to encode high definition videos in real-time when considering all target technologies.
引用
收藏
页码:5 / +
页数:3
相关论文
共 50 条
  • [31] A Hardware Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC Video Coding
    Chou, Yu-Lin
    Wu, Chung-Bin
    [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1915 - 1918
  • [32] Hardware-and-Memory-Sharing Architecture of Deblocking Filter for VP8 and H.264/AVC
    Wu, Chung-Bin
    Wang, Li-Hung
    Chou, Yu-Lin
    [J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 2017, 63 (03) : 216 - 224
  • [33] A high-throughput ASIC processor for 8 x 8 transform coding in H.264/AVC
    Michell, Juan A.
    Solana, Jose M.
    Ruiz, Gustavo A.
    [J]. SIGNAL PROCESSING-IMAGE COMMUNICATION, 2011, 26 (02) : 93 - 104
  • [34] A Multitransform Architecture for H.264/AVC High-Profile Coders
    Hwangbo, Woong
    Kyung, Chong-Min
    [J]. IEEE TRANSACTIONS ON MULTIMEDIA, 2010, 12 (03) : 157 - 167
  • [35] An Energy-Efficient 8x8 2-D DCT VLSI Architecture for Battery-Powered Portable Devices
    Livramento, Vinicius S.
    Moraes, Bruno G.
    Machado, Brunno A.
    Guentzel, Jose Luis
    [J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 587 - 590
  • [36] Motion Compensated Interpolation as a New Inter Coding Mode for 8x8 Macroblock Partitions in H.264/AVC B Slices
    Mys, Stefaan
    Slowack, Juergen
    Skorupa, Jozef
    Lambert, Peter
    Van de Walle, Rik
    [J]. Advances in Multimedia Information Processing - PCM 2008, 9th Pacific Rim Conference on Multimedia, 2008, 5353 : 168 - 177
  • [37] A 100-MHZ 2-D 8X8 DCT/IDCT PROCESSOR FOR HDTV APPLICATIONS
    MADISETTI, A
    WILLSON, AN
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1995, 5 (02) : 158 - 165
  • [38] A Low-Cost and High Efficiency Entropy Encoder Architecture for H.264/AVC
    Thiele, Cristiano C.
    Vizzotto, Bruno B.
    Martins, Andre L. M.
    da Rosa, Vagner S.
    Bampi, Sergio
    [J]. 2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 117 - 122
  • [39] 基于8×8的整数DCT快速计算的H.264/AVC软件实现
    贾昆霖
    [J]. 电子科技, 2017, (06) : 43 - 45
  • [40] A 250MHz optimized distributed architecture of 2D 8x8 DCT
    Peng Chungan
    Cao Xixin
    Yu Dunshan
    Zhang Xing
    [J]. ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 189 - 192