Analysis of Analog Comparators Using a 6-Bit Flash ADC Architecture

This paper is based on the design of a 6-bit, 2.5 GS/s flash analog-to-digital converter (ADC). Lower power consumption is a prime objective in this paper. As analog comparators are the basic building blocks of any ADC, this work makes an insight into static and dynamic latched analog comparators and also draws a comparison between different works based on various parameters. Thereafter, it uses the optimized design amongst these comparators for flash ADC design. Power-delay characteristics as well as noise parameters such as offset voltage and kickback noise of the comparators are calculated keeping 1 V supply and a detailed analysis is done. Simulations are made in CADENCE using 45 nm CMOS technology yielding a SNDR of 57.7 dB, SFDR of 61 dB and FoM of 15 fJ/conv-step at Nyquist frequency of 2.5 GHz with an input frequency of 20 MHz and supply voltage 1 V. The power consumption is seen to be 2.4 mW with INL and DNL of 0.4 LSB and 0.2 LSB at the sampling frequency of 2.5 GS/s.