High order 1-bit sigma delta ADC for multistandard GSM/UMTS radio receiver

被引：0
|
作者：
Rebai, C [1 ]
Ghazel, A [1 ]
Farhat, F [1 ]
机构：
[1] Ecole Super Commun, MEDIATROM Lab, SUP COM, Tunis, Tunisia
来源：
16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS | 2004年
关键词：
multi-standard radio; GSM; /UMTS; 1-bit Sigma Delta ADC; interpolative structure;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper deals with specification and design methodology of Analog to Digital Converter (ADC) stage for high dynamic range wide band Multi-standard Radio receiver. To respect high resolution requirements a Sigma Delta (YEA) modulator based ADC is proposed. A High dynamic range low complexity 1-bit Sigma Delta modulator is designed to guarantee high linearity for GSM/UMTS signals. Hence, a novel stable 3(rd) order 1-bit low-pass Sigma Delta modulator is defined. Simulation results show more than 90 dB dynamic ranges for GSM and 60 dB for UNITS.
引用
收藏
页码：128 / 131
页数：4
相关论文
共 50 条
  • [41] High Order PSK Modulation in Massive MIMO Systems With 1-Bit ADCs
    Sun, Bule
    Zhou, Yiqing
    Yuan, Jinhong
    Liu, Ya-Feng
    Wang, Lu
    Liu, Ling
    IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, 2021, 20 (04) : 2652 - 2669
  • [42] Digital High Order Multiplier-free Delta Sigma Modulator for Multistandard Fractional-N Frequency Synthesizer
    Ben-Romdhane, Manel
    Abeda, Aymen
    Rebai, Chiheb
    JOURNAL OF COMPUTERS, 2010, 5 (10) : 1494 - 1501
  • [43] High ACLR 1-bit direct radio frequency converter using symmetric waveform
    Maehata, Takashi
    Kameda, Suguru
    Suematsu, Noriharu
    European Microwave Week 2012: Space for Microwaves, EuMW 2012, Conference Proceedings - 42nd European Microwave Conference, EuMC 2012, 2012, : 1051 - 1054
  • [44] High ACLR 1-bit Direct Radio Frequency Converter Using Symmetric Waveform
    Maehata, Takashi
    Kameda, Suguru
    Suematsu, Noriharu
    2012 7TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2012, : 671 - 674
  • [45] Demodulation using High-Order Moments on a Stochastic Resonance Receiver with a Few-bit ADC
    Tatematsu, Akihiko
    Hatano, Hiroyuki
    Sanada, Kosuke
    Mori, Kazuo
    Tanaka, Hiroya
    Tadokoro, Yukihiro
    2022 IEEE 95TH VEHICULAR TECHNOLOGY CONFERENCE (VTC2022-SPRING), 2022,
  • [46] Zero-Delay Joint Source-Channel Coding with a 1-Bit ADC Front End and Receiver Side Information
    Varasteh, Morteza
    Rassouli, Borzoo
    Simeone, Osvaldo
    Gunduz, Deniz
    2016 IEEE INFORMATION THEORY WORKSHOP (ITW), 2016,
  • [47] High ACLR 1-bit Direct Radio Frequency Converter Using Symmetric Waveform
    Maehata, Takashi
    Kameda, Suguru
    Suematsu, Noriharu
    2012 42ND EUROPEAN MICROWAVE CONFERENCE (EUMC), 2012, : 1051 - 1054
  • [48] Zero-Delay Source-Channel Coding With a 1-Bit ADC Front End and Correlated Receiver Side Information
    Varasteh, Morteza
    Rassouli, Borzoo
    Simeone, Osvaldo
    Gunduz, Deniz
    IEEE TRANSACTIONS ON COMMUNICATIONS, 2017, 65 (12) : 5429 - 5444
  • [49] A 1V Second Order Delta Sigma ADC in 130nm CMOS
    LokeshKrishna, K.
    Ramashri, T.
    Reena, D.
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [50] AN FPGA BASED 1-BIT ALL DIGITAL TRANSMITTER EMPLOYING DELTA-SIGMA MODULATION WITH RF OUTPUT FOR SDR
    Shehata, Khaled A.
    Aboul-Dahab, Mohamed A.
    El Ramly, Salwa H.
    Hamouda, Karim A.
    SCS: 2008 2ND INTERNATIONAL CONFERENCE ON SIGNALS, CIRCUITS AND SYSTEMS, 2008, : 343 - +
12345