Analogue multiplexer for neural application in 180 nm CMOS technology

被引:0
|
作者
Zoladz, Miroslaw [1 ]
机构
[1] AGH Univ Sci & Technol, Dept Measurement & Instrumentat, Krakow, Poland
来源
PRZEGLAD ELEKTROTECHNICZNY | 2010年 / 86卷 / 11A期
关键词
neural recording; multi-channel ASIC; analogue multiplexer;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the architecture and the results of preliminary tests of the analogue multiplexer used in a multichannel ASIC (CMOS 180 nm) for recording signals from neural systems. The core of the ASIC consists of 64 analogue channels equipped with a band-pass filter (1 Hz to 10 kHz). In order to reduce the number of outputs, the 64 analogue channels are multiplexed to the single output by analogue 64: 1 multiplexer. The nominal frequency of the multiplexer is 2.5 MHz which results in 30 kHz sampling rate per single channel.
引用
收藏
页码:256 / 259
页数:4
相关论文
共 50 条
  • [1] Analogue Multiplexer for Neural Application in 180 nm CMOS Technology
    Zoladz, Miroslaw
    Grybos, Pawel
    Kachel, Maciej
    Kmon, Piotr
    Szczygiel, Robert
    MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, : 230 - 233
  • [2] Design of 64-channel Analogue Multiplexer for Neural Application in CMOS 180 nm Technology
    Kachel, Maciej
    Zoladz, Miroslaw
    Kmon, Plotr
    ICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGS, 2008, : 77 - 80
  • [3] 64 CHANNEL NEURAL RECORDING AMPLIFIER WITH TUNABLE BANDWIDTH IN 180 nm CMOS TECHNOLOGY
    Grybos, Pawel
    Kmon, Piotr
    Zoladz, Miroslaw
    Szczygiel, Robert
    Kachel, Maciej
    Lewandowski, Marian
    Blasiak, Tomasz
    METROLOGY AND MEASUREMENT SYSTEMS, 2011, 18 (04) : 631 - 643
  • [4] Integrated pH-Sensor for Medical Application in 180nm CMOS Technology
    Ouremchi, Mounir
    El Boutahiri, Abdelli
    Farah, Fouad
    El Khadiri, Karim
    Qjidaa, Hassan
    Lakhassassi, Ahmed
    Tahiri, Ahmed
    2019 4TH INTERNATIONAL CONFERENCE ON SMART AND SUSTAINABLE TECHNOLOGIES (SPLITECH), 2019, : 571 - 576
  • [5] Cryogenic characterization of 180 nm CMOS technology at 100 mK
    Huang, R. G.
    Gnani, D.
    Grace, C.
    Kolomensky, Yu G.
    Mei, Y.
    Papadopoulou, A.
    JOURNAL OF INSTRUMENTATION, 2020, 15 (06)
  • [6] Clock generator IP design in 180 nm CMOS technology
    Meng, Xu
    Lin, Fujiang
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 87 (03) : 369 - 377
  • [7] Clock generator IP design in 180 nm CMOS technology
    Xu Meng
    Fujiang Lin
    Analog Integrated Circuits and Signal Processing, 2016, 87 : 369 - 377
  • [8] CMOS Instrumentation Amplifier Design with 180nM Technology
    Gupta, Gaytri
    Tripathy, Mr.
    2014 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2014), 2014, : 1114 - 1116
  • [9] Comparative analysis of radiation tolerant analog circuit layout in 180 nm CMOS technology for space application
    Malik, Munish
    Prakash, Neelam R.
    Kumar, Ajay
    MICROELECTRONICS JOURNAL, 2023, 131
  • [10] SWITCHED-CAPACITOR FILTER DESIGN FOR ECG APPLICATION USING 180nm CMOS TECHNOLOGY
    Singh, Nitin
    Bansod, P. P.
    2017 INTERNATIONAL CONFERENCE ON RECENT INNOVATIONS IN SIGNAL PROCESSING AND EMBEDDED SYSTEMS (RISE), 2017, : 439 - 443