Balancing 3D Network-on-Chip Latency in Multi-Application Mapping based on M/G/1 Delay Model

Applying multi-applications to Network-on-Chip (NoC) communication structure has been receiving increasing attention recently. In this paper, we present a multi-application mapping algorithm for 3D NoC, which target to balance on-chip latency. Besides, we propose an accurate analytical delay model based on M/G/1 queuing model, which can be used to optimize performance and verify the constraint of delay in terms of flow level. In order to verify the efficiency of our proposed approach, several sets of multi-application benchmarks are evaluated. Simulation results show that the proposed algorithm reduces the maximum average latency by 18.32% and the standard deviation of latency by 15.57%.