A high performance multi-processor architecture for an on-board SAR processor system

The On-Board SAR Processing System Demonstrator (OSPS) is a modular part of an envisaged spaceborne Synthetic Aperture Radar (SAR) instrument. It provides the processing capability for on-board low resolution image generation in order to be able to realise a very efficient data reduction. The main goal of the OSPS development, under an ESA GSTP contract, is the realisation of a flight representative Multi-Processor Architecture for a conceivable SAR instrument. The system architecture consists of Processing Elements, each relying on the (re-) use of the existing Mosaic020 board and its module concept. A co-processor board called the FFT Extension board is attached to the Mosaic020 and increases dedicated signal processing performance using the FFT chip from doubleBW. The software running on the Processing Elements is separated into three levels: Low-level test and inspection software, Virtuoso real-time operating system software and application software. Technology development started in June 1999 and is scheduled to be completed in Q2 2001. This paper describes the Multi-Processor Architecture and the implementation of the Processing Elements and gives an overview of the software components.