A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation on FPGAs

被引：0
|
作者：
Saito, Hiroshi [1 ]
Hamada, Naohiro [1 ]
Yoneda, Tomohiro [2 ]
Nanya, Takashi [3 ]
机构：
[1] Univ Aizu, Aizu Wakamatsu, Fukushima, Japan
[2] Natl Inst Informat, Tokyo, Japan
[3] Univ Tokyo, Tokyo 1138654, Japan
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.
引用
收藏
页码：925 / 928
页数：4
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