Detailed implementation of asynchronous circuits on commercial FPGAs

This paper provides the essential details of implementing 4-phase bundled data and speed independent asynchronous circuits on FPGAs. The required Xilinx synthesis tools including attributes, constraints and hardware implementation of basic asynchronous elements like Cgate, delay line, and handshaking modules are discussed. Finally, two design and implementation examples of asynchronous circuits are introduced. In order to reduce area and energy overhead, an N-stage pipeline with internal loops is proposed and employed in asynchronous Fuzzy Logic Controller (FLC). It is observed that synchronous FLC operating at 100 MHz consumes 27% more dynamic power while occupying 23% fewer FPGA resources compared to its asynchronous counterpart. At the same time, the asynchronous circuit has obtained an improvement of 19% in FLC performance compared to synchronous FLC. The other implementation example explains the technical details of the design and implementation process of speed independent circuit using Petrify and ISE at the LUT level. Both design examples are implemented and tested successfully on FPGA board.