A Floorplan Method for Asynchronous Circuits with Bundled-data Implementation on FPGAs

被引：0
|
作者：
Saito, Hiroshi [1 ]
Hamada, Naohiro [1 ]
Yoneda, Tomohiro [2 ]
Nanya, Takashi [3 ]
机构：
[1] Univ Aizu, Aizu Wakamatsu, Fukushima, Japan
[2] Natl Inst Informat, Tokyo, Japan
[3] Univ Tokyo, Tokyo 1138654, Japan
来源：
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | 2010年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper proposes a floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. The proposed method minimizes the delay of the control circuit while considering timing constraints required for bundled-data implementation. Through the implementation of the proposed method, this paper evaluates the proposed method in terms of performance and area for generated floorplans.
引用
收藏
页码：925 / 928
页数：4
相关论文
共 50 条
  • [1] A Floorplan Method for ASIC Designs of Asynchronous Circuits with Bundled-data Implementation
    Iizuka, Minoru
    Saito, Hiroshi
    [J]. 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2013,
  • [2] A Behavioral Synthesis Method for Asynchronous Circuits with Bundled-data Implementation
    Hamada, Naohiro
    Shiga, Yuuki
    Saito, Hiroshi
    Yoneda, Tomohiro
    Myers, Chris
    Nanya, Takashi
    [J]. 2008 8TH INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN, PROCEEDINGS, 2008, : 50 - +
  • [3] A control circuit synthesis method for asynchronous circuits in bundled-data implementation
    Konishi, Takao
    Hamada, Naohiro
    Saito, Hiroshi
    [J]. 2007 CIT: 7TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY, PROCEEDINGS, 2007, : 847 - +
  • [4] Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs
    Bhardwaj, Kshitij
    Mantovani, Paolo
    Carloni, Luca P.
    Nowick, Steven M.
    [J]. 2019 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2019,
  • [5] A Tool Set for the Design of Asynchronous Circuits with Bundled-data Implementation
    Iizuka, Minoru
    Hamada, Naohiro
    Saito, Hiroshi
    Yamaguchi, Ryoichi
    Yoshinaga, Minoru
    [J]. 2011 IEEE 29TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2011, : 78 - 83
  • [6] A behavioral synthesis system for asynchronous circuits with bundled-data implementation
    Hamada, Naohiro
    Shiga, Yuki
    Konishi, Takao
    Saito, Hiroshi
    Yoneda, Tomohiro
    Myers, Chris
    Nanya, Takashi
    [J]. IPSJ Transactions on System LSI Design Methodology, 2009, 2 : 64 - 79
  • [7] Synthesis of Locally-Clocked Asynchronous Systems with Bundled-Data Implementation on FPGAs
    Garcia, Kledermon
    Oliveira, Duarte L.
    Curtinhas, Tiago
    d'Amore, Roberto
    [J]. 2014 IX SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC (SPL 2014), 2014,
  • [8] Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
    Hamada, Naohiro
    Saito, Hiroshi
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2012, E95C (04): : 506 - 515
  • [9] Static Timing Analysis of Asynchronous Bundled-Data Circuits
    Gimenez, Gregoire
    Cherkaoui, Abdelkarim
    Cogniard, Guillaume
    Fesquet, Laurent
    [J]. 2018 24TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC), 2018, : 110 - 118
  • [10] A cost-effective handshake protocol and its implementation for bundled-data asynchronous circuits
    Shimizu, M
    Abe, K
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (01) : 280 - 287
12345