Cross Domain Protection Analysis and Verification using Whole Chip ESD Simulation

被引：0

作者：

Okushima, Mototsugu ^{[1
]}

Kitayama, Tomohiro ^{[1
]}

Kobayashi, Susumu ^{[1
]}

Kato, Tetsuya ^{[1
]}

Hirata, Morihisa ^{[1
]}

机构：

[1] Renesas Elect Corp, Nakahara Ku, 1753 Shimonumabe, Kawasaki, Kanagawa, Japan

来源：

ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2010 | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A whole-chip simulation methodology of the full ESD paths including the full-chip power and ground wiring network has been established, and successfully demonstrated on products with several hundreds of pins. By checking voltage stress across cross domain circuits itself, marginal cross domain ESD design window in sub-100nm SoCs can be extended.

引用

页数：7

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