A Compact Threshold-Voltage Model of MOSFETs with Stack High-k Gate Dielectric

被引：2
|
作者：
Ji, F. [1 ]
Xu, J. P. [1 ]
Chen, J. J. [1 ]
Xu, H. X. [1 ]
Li, C. X. [2 ]
Lai, P. T. [2 ]
机构：
[1] Huazhong Univ Sci & Technol, Dept Elect Sci & Technol, Wuhan 430074, Peoples R China
[2] Univ Hong Kong, Dept Elect & Elect Engn, Hong Kong, Peoples R China
来源：
2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009) | 2009年
基金：
中国国家自然科学基金;
关键词：
MOSFET; Threshold voltage; stack gate dielectric;
D O I：
10.1109/EDSSC.2009.5394286
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
引用
收藏
页码：236 / +
页数：2
相关论文
共 50 条
  • [31] Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning
    Kirsch, P. D.
    Sivasubramani, P.
    Huang, J.
    Young, C. D.
    Park, C. S.
    Freeman, K.
    Hussain, M. M.
    Bersuker, G.
    Harris, H. R.
    Majhi, P.
    Lysaght, P.
    Tseng, H. -H.
    Lee, B. H.
    Jammy, R.
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 269 - +
  • [32] Observation of Slow Oxide Traps at MOSFETs Having Metal/High-k Gate Dielectric Stack in Accumulation Mode
    Cho, Heung-Jae
    Son, Younghwan
    Oh, Byoungchan
    Lee, Sanghoon
    Lee, Jong-Ho
    Park, Byung-Gook
    Shin, Hyungcheol
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (10) : 2697 - 2703
  • [33] Impact of High-K Gate Stack on Subthreshold Performance of Double-Gate (DG) MOSFETs
    Ekta Goel
    Silicon, 2022, 14 : 11539 - 11544
  • [34] Impact of High-K Gate Stack on Subthreshold Performance of Double-Gate (DG) MOSFETs
    Goel, Ekta
    SILICON, 2022, 14 (17) : 11539 - 11544
  • [35] High-k Gate Dielectric MOSFETs: Meeting the Challenges of Characterization and Modeling
    De Souza, M. M.
    Sicre, S. B. F.
    Casterman, D.
    SILICON NITRIDE, SILICON DIOXIDE, AND EMERGING DIELECTRICS 11, 2011, 35 (04): : 563 - 580
  • [36] High-K dielectrics for the gate stack
    Locquet, Jean-Pierre
    Marchiori, Chiara
    Sousa, Maryline
    Fompeyrine, Jean
    Seo, Jin Won
    Journal of Applied Physics, 2006, 100 (05):
  • [37] High-K dielectrics for the gate stack
    Locquet, Jean-Pierre
    Marchiori, Chiara
    Sousa, Maryline
    Fompeyrine, Jean
    Seo, Jin Won
    JOURNAL OF APPLIED PHYSICS, 2006, 100 (05)
  • [38] A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode
    Xu, J. P.
    Xiao, X.
    Lai, P. T.
    MICROELECTRONICS RELIABILITY, 2010, 50 (08) : 1081 - 1086
  • [39] Defect passivation with fluorine in a TaxCy/High-K gate stack for enhanced device threshold voltage stability and performance
    Tseng, HH
    Tobin, PJ
    Hebert, EA
    Kalpat, S
    Ramón, ME
    Fonseca, L
    Jiang, ZX
    Schaeffer, JK
    Hegde, RI
    Triyoso, DH
    Gilmer, DC
    Taylor, WJ
    Capasso, CC
    Adetutu, O
    Sing, D
    Conner, J
    Luckowski, E
    Chan, BW
    Haggag, A
    Backer, S
    Noble, R
    Jahanbani, M
    Chiu, YH
    White, BE
    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 713 - 716
  • [40] Threshold-voltage Modeling of double-gate MOSFETs by considering drain bias
    Choi, Byung-Kil
    Han, Kyoung-Rok
    Kim, Young Min
    Park, Ki-Heung
    Lee, Jong-Ho
    Roh, Tae Moon
    Kim, Jongdae
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2007, 51 : S275 - S279
12345