A Compact Threshold-Voltage Model of MOSFETs with Stack High-k Gate Dielectric

被引：2
|
作者：
Ji, F. [1 ]
Xu, J. P. [1 ]
Chen, J. J. [1 ]
Xu, H. X. [1 ]
Li, C. X. [2 ]
Lai, P. T. [2 ]
机构：
[1] Huazhong Univ Sci & Technol, Dept Elect Sci & Technol, Wuhan 430074, Peoples R China
[2] Univ Hong Kong, Dept Elect & Elect Engn, Hong Kong, Peoples R China
来源：
2009 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC 2009) | 2009年
基金：
中国国家自然科学基金;
关键词：
MOSFET; Threshold voltage; stack gate dielectric;
D O I：
10.1109/EDSSC.2009.5394286
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a compact threshold-voltage model is developed for stack high-k gate-dielectric MOSFET with a thin interlayer. The simulated results are in good agreement with 2-D simulations. The influences of k value of the interlayer on threshold behaviors are investigated in detail. A low-k interlayer can effectively improve the threshold-voltage behaviors. Furthermore, the ratio of low-k interlayer EOT (equivalent oxide thickness) to high-k layer EOT is optimized by considering both threshold-voltage roll-off and gate leakage current.
引用
收藏
页码：236 / +
页数：2
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