A 21mW 15b 48MS/s Zero-Crossing Pipeline ADC in 0.13μm CMOS with 74dB SNDR

被引：0

作者：

Chang, Dong-Young ^{[1
]}

Munoz, Carlos ^{[2
]}

Daly, Denis ^{[2
]}

Shin, Soon-Kyun ^{[2
]}

Guay, Kevin ^{[2
]}

Thurston, Thomas ^{[2
]}

Lee, Hae-Seung ^{[3
]}

Gulati, Kush ^{[1
]}

Straayer, Matthew ^{[2
]}

机构：

[1] Maxim Integrated, San Jose, CA 95134 USA

[2] Maxim Integrated, North Chelmsford, MA USA

[3] MIT, Cambridge, MA 02139 USA

来源：

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC) | 2014年 / 57卷

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：204 / +

页数：3

共 25 条

[1] A 21mW 8b 125MS/s ADC occupying 0.09mm2 in 0.13μm CMOS
Mulder, J
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Westra, JR
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Arslan, E
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van der Goes, FML
2004 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS, 2004, 47 : 260 - 261
[2] A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-μm CMOS Technology
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[3] A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology
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[7] A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS
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[8] A Calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s Four-Stage Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
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[9] A 4.86 mW 15-bit 22.5 MS/s Pipelined ADC with 74 dB SNDR in 90 nm CMOS Using Averaging Correlated Level Shifting Technique
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[10] A 28mw 10b 80ms/s pipelined ADC in 0.13μm CMOS
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