A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method

被引：24

作者：

Xing, Nan ^{[1
]}

Woo, Jong-Kwan ^{[1
]}

Shin, Woo-Yeol ^{[1
]}

Lee, Hyunjoong ^{[1
]}

Kim, Suhwan ^{[1
]}

机构：

[1] Seoul Natl Univ, Dept Elect Engn, Seoul 151744, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2010年 / 57卷 / 12期

关键词：

Delay-locked loop (DLL); fractional conversion scheme; input range; resolution; time-to-digital converter (TDC); triggerable voltage controlled oscillator (TVCO); CMOS; SCHEME;

D O I：

10.1109/TCSI.2010.2073810

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a time-to-digital converter (TDC) using a fractional difference conversion scheme. Two delay-locked loops (DLLs) provide negative feedbacks to stabilize the delays against process and ambient variations. In addition, by adopting the principles of cyclic Vernier delay line, the resolution is improved while dynamic range is significantly increased. The proposed TDC architecture is competitive in terms of resolution and power compared to the other DLL/PLL stabilized TDCs. The TDC designed and fabricated in 0.18 mu m CMOS process achieves a 14.6 ps resolution as well as a 50 ns dynamic range, while consuming 6.4 mW power.

引用

页码：3064 / 3072

页数：9

共 32 条

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