Digital System Design Using Standard NeuMOS Cells Applied in ADAS

被引：0

作者：

Medina-Santiago, A. ^{[1
]}

Vera Molina, Patricia E. ^{[2
]}

Reyes Barranca, Mario Alfredo ^{[3
]}

Zepeda Hernandez, J. A. ^{[2
]}

机构：

[1] Ctr Res Dev & Technol Innovat UDescartes, Tuxtla Gutierrez, Chiapas, Mexico

[2] TNM, Inst Tecnol Tuxtla Gutierrez, Tuxtla Gutierrez, Chiapas, Mexico

[3] Inst Politecn Nacl, Ctr Invest & Estudios Avanzados, Tuxtla Gutierrez, Chiapas, Mexico

来源：

CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2020年 / 39卷 / 07期

关键词：

Floating-gate transistor; Software-hardware-logic (SHL); NeuMOS; Floating-gate potential diagram (FPD); Standard cells; Digital electronic systems; ADAS; LOGIC-CIRCUIT;

D O I：

10.1007/s00034-019-01325-5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The design and implementation of digital systems with external configuration circuit-SHL (software-hardware-logic)-with standard cells based on floating-gate transistor (NeuMOS) and the implementation of the floating-gate potential diagram (FPD) to obtain Boolean functions are presented. External circuit configuration for designing digital systems of two and four bits reduces the number of transistors, as well as interconnection, and this can increase the speed of data processing; these results are helpful in growing applications like advanced driver assistance system (ADAS), where the number of sensors and processing time are increasing. Simulations results shown prove an effective reduction in transistor count, and a good performance of the system is demonstrated, as well.

引用

页码：3574 / 3594

页数：21

共 50 条

[21] Digital signal processing and digital system design using discrete cosine transform
Tseng, CJ
Aburdene, MF
2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5: SPEECH PROCESSING, 2005, : 557 - 560
[22] Time-Mode Analog-to-Digital Conversion Using Standard Cells
Unnikrishnan, Vishnu
Vesterbacka, Mark
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (12) : 3348 - 3357
[23] Clock multiplier using digital CMOS standard cells for high-speed digital communication systems
Lee, YK
Choi, SS
Kim, SG
Lee, JA
Kim, KS
ELECTRONICS LETTERS, 1999, 35 (24) : 2073 - 2074
[24] Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells
Weaver, Skyler
Hershberg, Benjamin
Moon, Un-Ku
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (01) : 84 - 91
[25] TRANSPUTERS APPLIED TO DIGITAL-FILTER DESIGN
GEORGE, AD
PROCEEDINGS : THE TWENTY-FIRST SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 1989, : 399 - 403
[26] STOCHASTIC TECHNIQUE APPLIED TO DIGITAL AUTOPILOT DESIGN
DANESI, A
MISSILI E SPAZIO, 1968, 10 (1-2): : 13 - &
[27] Construct digital management system of the performance test and design standard of the TTX using Model-Based Systems Engineering Approach
Song, Yongsoo
Han, sungho
Lee, su-gil
2007 INTERNATIONAL SYMPOSIUM ON LOGISTICS AND INDUSTRIAL INFORMATICS, 2007, : 81 - 85
[28] DESIGN OF A DIGITAL TRANSMULTIPLEXER USING STANDARD LOW-POWER SCHOTTKY TTL LOGIC
VERSVIK, I
IEEE TRANSACTIONS ON COMMUNICATIONS, 1982, 30 (07) : 1498 - 1505
[29] Design of A/D converters using current-mode standard cells
Ciota, Z
Jankowski, M
Napieralski, A
ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, : 24 - 27
[30] Experiences with a Practical Course on Circuit Design Using Standard Cells.
Tavangarian, D.
Bechtold, M.
Waldschmidt, K.
Informationstechnik it: Computer, Systeme, Anwendungen, 1986, 28 (03): : 168 - 176

← 1 2 3 4 5 →