Towards the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture

被引：0
|
作者：
Lopez, S. [1 ,2 ]
Kanstein, A. [3 ]
Lopez, J. F. [1 ,2 ]
Berekovic, M. [4 ]
Sarmiento, R. [1 ,2 ]
Mignolet, J. -Y. [4 ]
机构：
[1] Univ Las Palmas Gran Canaria, DIEA, E-35017 Las Palmas Gran Canaria, Spain
[2] Univ Las Palmas Gran Canaria, Inst Appl Microelect IUMA, E-35017 Las Palmas Gran Canaria, Spain
[3] Freescale Inc, Toulouse, France
[4] IMEC, Leuven, Belgium
来源：
VLSI CIRCUITS AND SYSTEMS III | 2007年 / 6590卷
关键词：
H.264/AVC; reconfigurable architecture; coarse-grained array; motion compensation; adaptive deblocking filter; ADRES; DRESC;
D O I：
10.1117/12.722042
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor.
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页数：10
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