Real-time image processing with dynamically reconfigurable architecture

During the last few years, many architectures using processors and/or field programmable gate arrays (FPGA) were built to accelerate computationally complex problems. The processors allow a high degree of flexibility, whilst the FPGA implementation might be considerably faster. In spite of the possibility of reconfiguring the conventional FPGA an unlimited number of time, many of these architectures were built to compute a single application. If the FPGA is reconfigured several times to execute various algorithms, the configuration time increases and degrades global performances. In this paper, an architecture dedicated to real-time image processing using the AT40K reconfigurable FPGA family is presented (ARDOISE project(1)). We discuss Dynamic Reconfiguration (or Run-Time Reconfiguration), a technique based on the reuse of the same device (an FPGA configured on the fly) by scheduling the execution of different algorithms building an application. The techniques and the tools developed to test and use the system are described. (C) 2003 Elsevier Ltd. All rights reserved.