A Real-Time Reconfigurable Architecture for Face Detection

This paper presents a new hardware architecture for pattern detection and classification specific for human face detection including raw image acquisition, integral image creation, window extraction, pyramid generation, and detection algorithms in simultaneous steps. The detection part of the face is implemented in a reconfigurable way by providing different paths for either Viola-Jones or block LBP algorithms. The Adaboost algorithm using Haar features are calculated in parallel being implemented in hardware. The reconfigurability of the hardware relates to the implementation of high level commands which can switch between different algorithms for face detection as well as between various paths used for image acquisition. As such, the architecture can be used by either still or video-based face detection which very important for face tracking. The performance of the architecture depends very much of the FPGA device used. An implementation on Xilinx Spartan 6, ZYNQ, and Xilinx Virtex-7 has been accomplished. The performances of the two implementations are compared in the end of this paper.