Modified Architecture for Real-Time Face Detection using FPGA

被引：0
|
作者：
Das, Suraj [1 ]
Jariwala, Atit [1 ]
Pinalkumar [1 ]
机构：
[1] Sardar Vallabhbhai Natl Inst Technol, Dept Elect Engn, Surat, India
来源：
3RD NIRMA UNIVERSITY INTERNATIONAL CONFERENCE ON ENGINEERING (NUICONE 2012) | 2012年
关键词：
AdaBoost; Face detection; FPGA; Haar classifier; real-time system;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we introduce modified hardware architecture with key features of lessening the resource usage of the FPGA and elevating the face detection frame rate. The system is based on well-known Viola Jones Frame-work which consists of AdaBoost algorithm integrated with Haar features. We also enlist the modification in hardware design techniques to achieve more parallel processing and higher detection speed of the system. The system implemented on Xilinx Virtex-5 FPGA development board outputs a high face detection rate (91.3%) at 60 frame/second for a VGA (640 x 480) video source. The power consumption of the implementation is 2.1 W.
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页数：5
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