Memory chip BIST architecture

This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is "free" for some faults during test. 4 is never subject to aliaising. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether ct fault has been detected. Thus, the storage requirement for the implementation of the test scheme as zero. 8. If used as a built-in feature, the hardware overhead is very low.