Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology

被引：0
|
作者：
Li, Hong-Chen [1 ]
Xiao, Li-Yi [1 ]
Li, Jie [1 ]
Liu, He [1 ]
机构：
[1] Harbin Inst Technol, Microelect Ctr, Harbin 150001, Heilongjiang, Peoples R China
来源：
2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2019年
关键词：
LATCH DESIGN; CELL;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We proposed a novel High Performance and Cost Effective (HPCE) soft error resilient Flip-Flop (FF) in 65nm technology in this paper. By adding XOR gates and the shadow latch controlled by pulsed clock, the proposed FF can detect and correct the SETs, the SEUs, and the TEs on the fly. Simulation results have indicated that compared with other state of the art soft error hardened FFs, the HPCE FF has higher reliability, lower cost and higher performance.
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页数：4
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